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VIA Technologies Cuts Silicon Test Time by 11X Using Synopsys’ DFTMAX Ultra

Synopsys, provider of software, IP and Services to accelerate innovation in chips and electronic systems has announced that Via Technologies, supplier of power efficient x86 processor platforms, successfully taped out a system on chip design using Synopsys DFTMAX  Ultra Compression, meeting test time and quality goals.

The need to shorten test time in conjunction with increasing design complexity drove VIA Technologies requirement for higher test compression. DFTMAX Ultra and Synopsys’ TetraMAX ATPG delivered 11X higher compression while maintaining high test quality and requiring only one week to deploy. As a result, VIA Technologies has standardized on DFTMAX Ultra and TetraMAX for all pin-limited designs.images

“DFTMAX Ultra delivered 11X higher compression on our pin-limited design, which allowed us to meet our manufacturing test goals,” said JC Chen, design service manager of the Hardware Technology Development Center at VIA Technologies. “We were able to incorporate DFTMAX Ultra into our design flows within a few days without impacting our stringent schedules. Due to the superior results DFTMAX Ultra delivers, we will be using it for all our pin-limited designs.”

Design teams are under pressure to ensure high manufacturing defect coverage while facing multiple factors that reduce the number of pins available for test. These include designs such as mobile applications that are pin-limited, large SoCs that have few pins per core for test access, as well as a technique known as multisite testing that checks for defects across multiple dies simultaneously.

Companies like VIA Technologies are deploying DFTMAX Ultra to address the increased costs typically associated with pin-limited testing. By achieving significantly higher compression than previous technologies, DFTMAX Ultra enables high defect coverage utilizing as few as one pair of test pins. Built into Design Compiler, DFTMAX Ultra synthesizes the test compression logic into a design, then sets up Synopsys TetraMAX ATPG to generate high defect-coverage, power-aware test programs.

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