Synopsys, Inc. has announced the availability of the 2014.09 release of its IC Compilerplace and route product, a key component of Synopsys’ GalaxyDesign Platform. The latest release continues the well-established trend of enabling leading-edge system on a chip (SoC) design through improved quality of results, faster convergence and advanced support for FinFET-based design.
New capabilities include look-ahead technologies and enhanced concurrent clock and data optimization (CCD) for a frequency boost on high-performance designs, accelerated design closure using Synopsys’ PrimeTime physically-aware engineering change order (ECO) and cutting-edge optimizations to reduce power and improve timing for FinFET-based emerging silicon technologies.
“Cavium is a market leader in high-performance processors used to power a wide array of networking applications around the world,” said Anil Jain, corporate vice president, IC engineering at Cavium. “We have long relied on IC Compiler to provide us with new, leading-edge technologies that enable us to achieve the best performance across all our complex and challenging designs. The latest release helps us further our leadership position in the marketplace.”
The2014.09 release delivers more look-ahead technologies including accounting for downstream effects such as crosstalk at the pre-route stage and performing virtual optimizations during placement for improved timing.CCD, a key technology to increase on-chip clock frequency, has been augmented to more accurately account for the timing impact of signal integrity and detailed wiring, yielding up to five percent faster circuits.
IC Compiler, working hand-in-hand with Synopsys’ PrimeTime, provides a highly efficient physically-aware ECO solution to minimize the number of ECOs and implement them with minimal layout perturbation. It also has a consistency checker that automatically identifies and resolves differences between the signoff and place-and-route environments to improve signoff correlation.
2014.09 release addresses several second order effects that are critical to delivering quality results on FinFET-based designs. In this software release, dynamic power is optimized simultaneously with leakage power, timing, area and routability in order to achieve the maximum total power savings and meet timing.