Developed by Intel, the QuickPath Interconnect (QPI) is a point-to-point processor interconnect. It replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and the availability of bandwidth. A significantly revamped version is QPI 1.1, introduced with Sandy Bridge-EP (Romley platform). In the future Skylake EX/EP Xeon processors, QPI will be replaced by Intel UltraPath Interconnect (UPI) based on LGA 3647 socket.
The QPI is an element of the system architecture that Intel calls the QuickPath architecture. It implements what Intel calls QuickPath technology. A single QPI is used to connect the processor to the IO Hub in its simplest form on a single-processor motherboard. Separate QPI link pairs connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard in more complex instances of the architecture, allowing all of the components to access other components via the network. In the case of HyperTransport, the QuickPath Architecture assumes that the processors will have integrated memory controllers, and enables a non-uniform memory access (NUMA) architecture.
Operating at a clock rate of 2.4 GHz, 2.93 GHz, 3.2 GHz, 4.0 GHz or 4.8 GHz, QPI is specified as a five-layer architecture, with separate physical, link, routing, transport, and protocol layers. The transport layer is not present in devices intended only for point-to-point QPI use with no forwarding, such as the Core i7-9xx and Xeon DP processors, and the routing layer is minimal.